1. Field of the Invention
The present invention relates to a cache control technology, and it particularly relates to prefetch command control method and apparatus and cache memory control apparatus.
2. Description of the Related Art
One aspect of referencing main memory such as I/O and DRAM by computer processor is locality. By taking advantage of this locality and copying frequently referenced data stored in main memory into the cache memory, which is a high speed accessible small capacity internal memory, and accessing the main memory through this cache memory, it is possible to reduce latency for memory access. As the processing performance of processors has improved, the importance of cache memory is also becoming greater in terms of high-speed data supply to the processor.
When the cache is hit, the processor can obtain necessary data at the access speed of the cache memory. But, in the case of a cache miss, the processor needs to stop program execution while data is transferred from the main memory to the cache memory. A cache miss occurs when a copy of the data in the main memory is not existent in the cache memory as a result of cached data being cached out due to a shortage of cache capacity or the data being accessed being referenced for the first time. In the former case, the problem can be avoided by increasing the cache memory capacity. However, when the cache memory capacity increases, the cost increases so that it is difficult to significantly increase the capacity. In the latter case, the problem can be avoided by using a method called prefetch, by which data expected to be used in the future are transferred to the cache memory in advance of execution.
Prefetch is an effective means to further reduce memory access time. However, a speculative prefetch may actually lower the efficiency of the cache memory. This is because if prefetch is used too often when the cache memory capacity is small, formerly cached data is cached out by the prefetched data. Since there is no definite guideline for which situation and time a prefetch command shall be issued, while many processors are prefetch command compatible, the actual state is that prefetch commands are often not used effectively.